View 74VCX32373_312933.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Preliminary
74VCX32373 Low Voltage 32-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs (Preliminary)
February 2001 Revised August 2001
74VCX32373 Low Voltage 32-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs (Preliminary)
General Description
The VCX32373 contains thirty-two non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear to be transparent to the data when the Latch enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. The 74VCX32373 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The 74VCX32373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
s 1.65V-3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD (In to On) 3.0 ns max for 3.0V to 3.6V VCC 3.4 ns max for 2.3V to 2.7V VCC 6.8 ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Support live insertion and withdrawal (Note 1) s Static Drive (IOH/IOL)
24 mA @ 3.0V VCC 18 mA @ 2.3V VCC 6 mA @ 1.65V VCC
s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 mA s ESD performance: Human body model > 2000V Machine model > 200V s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Ordering Number Package Number 74VCX32373GX (Note 2) BGA96A Package Description 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL]
Note 2: BGA package available in Tape and Reel only.
Logic Symbol
(c) 2001 Fairchild Semiconductor Corporation
DS500567
www.fairchildsemi.com
Preliminary 74VCX32373 Connection Diagram
Pin Assignment for FBGA
Pin Descriptions
Pin Names OEn LEn I0-I31 O0-O31 Description Output Enable Input (Active LOW) Latch Enable Input Inputs Outputs
FBGA Pin Assignments
1 A B C D E F G H (Top Thru View) J K L M N P R T O1 O3 O5 O7 O9 O11 O13 O14 O17 O19 O21 O23 O25 O27 O29 O30 2 O0 O2 O4 O6 O8 O10 O12 O15 O16 O18 O20 O22 O24 O26 O28 O31 3 OE1 GND VCC GND GND VCC GND OE2 OE3 GND VCC GND GND VCC GND OE4 4 LE1 GND VCC GND GND VCC GND LE2 LE3 GND VCC GND GND VCC GND LE4 5 I0 I2 I4 I6 I8 I10 I12 I15 I16 I18 I20 I22 I24 I26 I28 I31 6 I1 I3 I5 I7 I9 I11 I13 I14 I17 I19 I21 I23 I25 I27 I29 I30
Truth Tables
Inputs LE1 X H H L OE1 H L L L Inputs LE2 X H H L
H L X
Outputs I0-I7 X L H X O0-O7 Z L H O0 Outputs I8-I15 X L H X O8-O15 Z L H O0 LE4 X H H L LE3 X H H L
Inputs OE3 H L L L Inputs OE4 H L L L I24-I31 X L H X I16-I23 X L H X
Outputs O16-O23 Z L H O0 Outputs O24-O31 Z L H O0
OE2 H L L L
= HIGH Voltage Level = LOW Voltage Level = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance O0 = Previous O0 before HIGH-to-LOW of Latch Enable
www.fairchildsemi.com
2
Preliminary
74VCX32373
Functional Description
The 74VCX32373 contains thirty-two edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 32-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the In enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its I input changes. When LEn is LOW, the latches store information that was present on the I inputs a setup time preceding the HIGH-to-LOW transition on LEn. The 3STATE outputs are controlled by the Output Enable (OEn) input. When OEn is LOW the standard outputs are in the 2state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.
Logic Diagrams
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
www.fairchildsemi.com
Preliminary 74VCX32373 Absolute Maximum Ratings(Note 3)
Supply Voltage (VCC ) DC Input Voltage (VI) Output Voltage (VO) Outputs 3-STATED Outputs Active (Note 4) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V VO > VCC DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (ICC or GND) Storage Temperature Range (TSTG)
-0.5V to +4.6V -0.5V to +4.6V -0.5V to +4.6V -0.5V to VCC +0.5V -50 mA -50 mA +50 mA 50 mA 100 mA -65C to +150C
Recommended Operating Conditions (Note 5)
Power Supply Operating Data Retention Only Input Voltage Output Voltage (VO) Output in Active States Output in "OFF" State Output Current in IOH/IOL VCC = 3.0V to 3.6V VCC = 2.3V to 2.7V VCC = 1.65V to 2.3V Free Air Operating Temperature (TA) Minimum Input Edge Rate (t/V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V
Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 4: IO Absolute Maximum Rating must be observed. Note 5: Floating or unused inputs must be held HIGH or LOW.
1.65V to 3.6V 1.2V to 3.6V
-0.3V to +3.6V
0V to VCC 0.0V to 3.6V
24 mA 18 mA 6 mA -40C to +85C
DC Electrical Characteristics (2.7V < VCC 3.6V)
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = -100 A IOH = -12 mA IOH = -18 mA IOH = -24 mA VOL LOW Level Output Voltage IOL = 100 A IOL = 12 mA IOL = 18 mA IOL = 24 mA II IOZ IOFF ICC ICC Input Leakage Current 3-STATE Output Leakage Power-OFF Leakage Current Quiescent Supply Current Increase in ICC per Input 0 VI 3.6V 0 VO 3.6V VI = VIH or VIL 0 (VI, VO) 3.6V VI = VCC or GND VCC (VI, VO) 3.6V (Note 6) VIH = VCC - 0.6V
Note 6: Outputs disabled or 3-STATE only.
Conditions
VCC (V) 2.7-3.6 2.7-3.6 2.7-3.6 2.7 3.0 3.0 2.7-3.6 2.7 3.0 3.0 2.7-3.6 2.7-3.6 0 2.7-3.6 2.7-3.6 2.7-3.6
Min 2.0
Max
Units V
0.8 VCC - 0.2 2.2 2.4 2.2 0.2 0.4 0.4 0.55 5.0 10 10 20 20 750
V V V V V V V V V A A A A A A
www.fairchildsemi.com
4
Preliminary
74VCX32373
DC Electrical Characteristics (2.3V VCC 2.7V)
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = -100 A IOH = -6 mA IOH = -12 mA IOH = -18 mA VOL LOW Level Output Voltage IOL = 100 A IOL = 12 mA IOL = 18 mA II IOZ IOFF ICC Input Leakage Current 3-STATE Output Leakage Power-OFF Leakage Current Quiescent Supply Current 0 VI 3.6V 0 VO 3.6V VI = V IH or VIL 0 (VI, VO) 3.6V VI = V CC or GND VCC (VI, VO) 3.6V (Note 7)
Note 7: Outputs disabled or 3-STATE only.
Conditions
VCC (V) 2.3 - 2.7 2.3 - 2.7 2.3 - 2.7 2.3 2.3 2.3 2.3 - 2.7 2.3 2.3 2.3 - 2.7 2.3 - 2.7 0 2.3 - 2.7 2.3 - 2.7
Min 1.6
Max
Units V
0.7 VCC - 0.2 2.0 1.8 1.7 0.2 0.4 0.6 5.0 10 10 20 20
V V V V V V V V A A A A A
DC Electrical Characteristics (1.65V VCC < 2.3V)
Symbol VIH VIL VOH VOL II IOZ IOFF ICC Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Leakage Current 3-STATE Output Leakage Power-OFF Leakage Current Quiescent Supply Current IOH = -100 A IOH = -6 mA IOL = 100 A IOL = 6 mA 0 VI 3.6V 0 VO 3.6V VI = V IH or VIL 0 (VI, VO) 3.6V VI = V CC or GND VCC (VI, VO) 3.6V (Note 8)
Note 8: Outputs disabled or 3-STATE only.
Conditions
VCC (V) 1.65 - 2.3 1.65 - 2.3 1.65 - 2.3 1.65 1.65 - 2.3 1.65 1.65 - 2.3 1.65 - 2.3 0 1.65 - 2.3 1.65 - 2.3
Min 0.65 x VCC
Max
Units V
0.35 x V CC VCC - 0.2 1.25 0.2 0.3 5.0 10 10 20 20
V V V V V A A A A A
5
www.fairchildsemi.com
Preliminary 74VCX32373 AC Electrical Characteristics (Note 9)
T A = -40C to +85C, CL = 30 pF, RL = 500 Symbol Parameter V CC = 3.3V 0.3V Min tPHL, tPLH tPHL, tPLH tPZL, tPZH tPLZ, tPHZ tS tH tW Propagation Delay In to On Propagation Delay LE to On Output Enable Time Output Disable Time Setup Time Hold Time Pulse Width 0.8 0.8 0.8 0.8 1.5 1.0 1.5 Max 3.0 3.0 3.5 3.5 V CC = 2.5V 0.2V Min 1.0 1.0 1.0 1.0 1.5 1.0 1.5 Max 3.4 3.9 4.6 3.8 V CC = 1.8V 0.15V Min 1.5 1.5 1.5 1.5 2.5 1.0 4.0 Max 6.8 7.8 9.2 6.8 ns ns ns ns ns ns ns Units
Note 9: For CL = 50PF, add approximately 300 ps to the AC maximum specification.
Dynamic Switching Characteristics
Symbol VOLP Parameter Quiet Output Dynamic Peak VOL Conditions CL = 30 pF, VIH = VCC, VIL = 0V VCC (V) 1.8 2.5 3.3 VOLV Quiet Output Dynamic Valley VOL CL = 30 pF, VIH = VCC, VIL = 0V 1.8 2.5 3.3 VOHV Quiet Output Dynamic Valley VOH CL = 30 pF, VIH = VCC, VIL = 0V 1.8 2.5 3.3 TA = +25C Typical 0.25 0.6 0.8 -0.25 -0.6 -0.8 1.5 1.9 2.2 V V V Units
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter Conditions VCC = 1.8V, 2.5V or 3.3V, VI = 0V or VCC VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V VI = 0V or VCC, f = 10 MHz, VCC = 1.8V, 2.5V or 3.3V TA = +25C Typical 6 7 20 Units pF pF pF
www.fairchildsemi.com
6
Preliminary
74VCX32373
AC Loading and Waveforms
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
SWITCH Open 6V at VCC = 3.3 0.3V; VCC x 2 at VCC = 2.5 0.2V; 1.8V 0.15V GND FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output HIGH Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output LOW Enable and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and trec Waveforms Symbol Vmi Vmo VX VY
FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic VCC
3.3V 0.3V 1.5V 1.5V VOL +0.3V VOH -0.3V
2.5V 0.2V VCC/2 VCC/2 VOL +0.15V VOH -0.15V
1.8V 0.15V VCC/2 VCC/2 VOL +0.15V VOH -0.15V
7
www.fairchildsemi.com
Preliminary 74VCX32373 Low Voltage 32-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs (Preliminary) Physical Dimensions inches (millimeters) unless otherwise noted
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA96A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

▲Up To Search▲

Price & Availability of 74VCX32373

	To Download 74VCX32373 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .